Multiport arrays are important for computer systems which require concurrent access to a data storage at the same time. This in particular applies to parallel systems comprising a large number of processors. In such systems typically a large amount of instructions and data are processed in parallel including a multiple access to the same memory.
Various dynamic static multiport memory cells are known for the use in random access memory arrays in the VLSI system design. For example, EP 0 591 752 discloses a dynamic multiport memory cell comprising pairs of memory cells at the intersections of a pair of bit lines and a pair of word lines. This device uses a random access port and a serial access port. Data are transmitted from the random access port to serial access port via a data register.
U.S. Pat. No. 5,754,468 discloses a static random access memory cell which comprises three P-type transistors and three N-type transistors to form a two port memory cell which can be configured to perform as a one port or two port memory cell. Additional ports can be added to allow, for example, the use of the cell in a three port register array.
Implementations of multiport arrays require normally as many input/output terminals as the number of concurrent accesses occur at the same time. Major problems of the physical implementation of multiport arrays are the available chip area per memory cell and the power consumption. The more ports an array has the more chip area is needed for the implementation where the increase follows a square function. These problems usually require a custom design which is time consuming and inflexible for being extended or otherwise changed later one.
Real multiport arrays have the structure of a matrix of signal lines, one of which selecting a cell and another one for reading/writing the data, where each cross lays above an storage element. Increasing the number of ports from 1 to 2 would mean to design a matrix of 2 by 2 signal lines with the same single bit as storage element below this matrix and so on. This leads to a rapid increase of the cell area when the number of ports is increased.
Conventional implementation techniques of real multiport arrays use a matrix structure which results in an area increase function x2 (x=number of ports). The exact number depends on the ratio silicon to wire and is also dependant whether a SRAM cell or a register cell is used. Data out control and signal lines for data out ports are combined with the storage elements within the same area.
There are also possibilities to built logical n-port arrays by implementing n physical single port arrays which hold the same data. It needs n times the area of the single port array.
If the array operation cycle is long enough it is also possible to read the storage elements several times in sequence within one cycle. In this manner a logical n-port array can be implemented as a single port array which is read n times in order to provide the same information as a real n port array.
It is also known to use multiport structures in programmable logic arrays (PLA). U.S. Pat. No. 3,975,623 discloses a PLA which comprises a segmented OR part where the segments are arranged at opposite sides of an AND part of the array. The output lines of the AND part are splitted into two groups of ports each of which is connected to the segments of the OR array.